The present invention relates to a nonvolatile semiconductor memory device using SOI (silicon on insulator) and, in particular, to miniaturization and high performance of a nonvolatile semiconductor memory device.
An EEPROM (electrically erasable and programmable ROM), which is one of nonvolatile semiconductor memory devices, will be described hereinafter. It is known that the EEPROM utilizes memory cells each having a MOS transistor structure of a layered structure of a floating gate (charge storing layer) and a control gate.
FIGS. 1A and 1B are cross-sectional views of a memory cell used for an EEPROM having a MOS transistor structure of a floating gate and a control gate.
As illustrated in FIG. 1A, an element isolation insulation film 102 is formed in an element isolation region on a silicon semiconductor substrate 101. A p.sup.+ diffusion layer 103, serving as a channel stopper, is formed immediately under the film 102. A thin gate insulation film 104 through which a tunnel current is allowed to flow, is formed in an active region of the substrate 101. A floating gate electrode (charge storing layer) 105 is formed on the film 104, and a control gate 107 is formed on the electrode 105 with an insulation film 106 interposed therebetween. As shown in FIG. 1B, an n.sup.+ diffusion layer 108 serving as a source or a drain of the memory cell, is formed in self-alignment by ion implantation using the floating gate electrode 105 and control gate 107 as a mask.
Conventionally, a field oxide film, which is formed by thermal oxidation of the silicon semiconductor substrate 101, is used for the element isolation insulation film 102. LOCOS (Local Oxidation of Silicon) is well knows as a method for forming the field oxide film. In the LOCOS, using a silicon nitride film formed on the silicon semiconductor substrate as a mask, a thick silicon oxide film (element isolation insulation film) is formed by thermal oxidation in a region which is not covered with the silicon nitride film.
However, when the element isolation insulation film (field oxide film) 102 is formed by the LOCOS, a wedged portion called a bird's beak is formed in the film 102. It is well known that the bird's beak makes the dimensions of the actually-formed element isolation insulation film 102 greater than those of a design for the element isolation region. Therefore, in general, the LOCOS is not suitable for forming a very small element isolation region of 0.5 .mu.m or less.
According to the LOCOS, since almost lower half of the element isolation insulation film 102 extends to the inside of the silicon semiconductor substrate 1 from the surface thereof, the element isolation ability is very poor. In this respect, too, in LOCOS, it is very difficult to narrow an interval between isolated elements.
Furthermore, according to the LOCOS, part of the element isolation insulation film 102, which protrudes from the surface of the silicon substrate 101, causes a step on the substrate 101. This step decreases a processing margin of a pattern having very small dimensions in a photolithographic process.
As an element isolation technique for resolving the above problems, a trench element isolation method (which is called "shallow trench isolation") is known in which a trench is formed in a silicon semiconductor substrate and filled with insulating materials.
FIG. 2 is a cross-sectional view of a memory cell of a nonvolatile semiconductor memory device adopting the trench element isolation method.
The trench element isolation method has the following advantages. Since the actual dimensions are almost equal to those of a design, the method is more suitable for forming a miniaturized element isolation region than the LOCOS. Since almost all the element isolation insulation film 102 is formed inside the silicon semiconductor substrate 101, the method is excellent in element isolation ability. since, furthermore, the surface of the element isolation insulation film 102 is flat and almost flush with that of the silicon semiconductor substrate 101, the film 102 does not cause a step on the substrate 101.
In the memory cell shown in FIG. 2, the element isolation insulation film 102 is formed in selfalignment with a floating gate electrode (charge storing layer) 105; therefore, the floating gate electrode 105 has no portion (wing portion) overlapping the film 102. The width of the film 102 thus depends upon only the element isolation characteristics.
However, even in the trench element isolation method, the element isolation ability depends upon an interval between adjacent elements (memory cells) or the width of the element isolation insulation film 102 (width of the trench) and the depth thereof (depth of the trench). If the width of the film 102 is decreased, the depth thereof has to be increased in order to achieve an adequate element isolation ability. This means that the aspect ratio of the trench is increased; thus, it is very difficult to achieve a process of etching for forming the trench and that of burying insulating materials into the trench.
Let us consider the performance of a transistor constituting a memory cell. The planar technique of forming an element by thermally oxidizing the surface of a silicon substrate and exposing the surface of an element region, is remarkably effective in increasing the size of an integrated circuit and the packing density thereof. However, as the miniaturization and integration of semiconductor elements increase to gain their operation speed, the influence of parasitic capacitance between the silicon semiconductor substrate and the metal wiring between the elements has recently become so great.
The product of a voltage applied to the semiconductor elements, power consumption due to a current caused to flow by the voltage, and delay time of the semiconductor elements, is fixed as a CR time constant of parasitic capacitance C and parasitic resistance R. Therefore, the parasitic capacitance C and parasitic resistance R have to be decreased in order to perform a high-speed operation while lowering the power consumption.
The wiring resistance, contact resistance, element resistance, etc., which cause the parasitic resistance R, are greatly reduced by improvement in process. On the other hand, the parasitic capacitance C is a very serious problem because it increases more greatly as an interval between the elements becomes narrower and narrower. Since, for example, the capacitance between wirings is abruptly. increased by miniaturization, a space between layers needs to be filled with low-dielectric insulative materials. Since, however, the elements are formed on the silicon semiconductor substrate, the parasitic capacitance between the substrate and wiring cannot be eliminated.
In the conventional nonvolatile semiconductor memory device described above, it is very difficult to form an element isolation insulation film having an adequate element isolation characteristic by increasing the size and packed density of an element, and the parasitic resistance and parasitic capacitance of the element are increased.